A Processor-In-Memory Architecture for Multimedia Compression

@article{citeulike:1273109, abstract = {<para> This paper presents the design and development of a novel, low-complexity processor-in-memory (PIM) architecture for image and video compression. By integrating a novel-processing element with SRAM, bandwidth is improved and latency is greatly reduced. This paper also presents PIM design techniques for reduced power, area, and complexity for rapid deployment and reduced cost. A design methodology is presented and followed by an analysis of the processing element performance and capabilities. The proposed datapath solution delivers between 2 to 40 times higher performance compared to other presented solutions. The architecture executes a discrete cosine and wavelet transforms achieving up to 40\% higher throughput per watt and occupying as little as 0.9\% area compared to a commercial digital signal processing and other application-specified integrated circuit implementations while maintaining precision. A comprehensive comparative analysis is also provided. The proposed processor-in-memory is implemented in 1.8-V 0.18-<formula formulatype="inline"><tex>\$mu\$</tex></formula>m CMOS technology and operates with a 300-MHz clock. </para>}, author = {Jasionowski, Brandon J. and Lay, Michelle K. and Margala, Martin }, citeulike-article-id = {1273109}, doi = {http://dx.doi.org/10.1109/TVLSI.2007.893672}, journal = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on}, number = {4}, pages = {478--483}, posted-at = {2007-05-03 04:55:06}, priority = {2}, title = {A Processor-In-Memory Architecture for Multimedia Compression}, url = {http://dx.doi.org/10.1109/TVLSI.2007.893672}, volume = {15}, year = {2007} }

TY - JOUR ID - citeulike:1273109 L3 - citeulike-article-id:1273109 TI - A Processor-In-Memory Architecture for Multimedia Compression JF - Very Large Scale Integration (VLSI) Systems, IEEE Transactions on VL - 15 IS - 4 SP - 478 EP - 483 N2 - <para> This paper presents the design and development of a novel, low-complexity processor-in-memory (PIM) architecture for image and video compression. By integrating a novel-processing element with SRAM, bandwidth is improved and latency is greatly reduced. This paper also presents PIM design techniques for reduced power, area, and complexity for rapid deployment and reduced cost. A design methodology is presented and followed by an analysis of the processing element performance and capabilities. The proposed datapath solution delivers between 2 to 40 times higher performance compared to other presented solutions. The architecture executes a discrete cosine and wavelet transforms achieving up to 40% higher throughput per watt and occupying as little as 0.9% area compared to a commercial digital signal processing and other application-specified integrated circuit implementations while maintaining precision. A comprehensive comparative analysis is also provided. The proposed processor-in-memory is implemented in 1.8-V 0.18-<formula formulatype="inline"><tex>$mu$</tex></formula>m CMOS technology and operates with a 300-MHz clock. </para> AU - Jasionowski, Brandon AU - Lay, Michelle AU - Margala, Martin PY - 2007/// UR - http://dx.doi.org/10.1109/TVLSI.2007.893672 ER -