A 500-Mb/s soft-output Viterbi decoder

by: Engling Yeo, SA Augsburger, WR Davis, B Nikolic

Solid-State Circuits, IEEE Journal of, Vol. 38, No. 7. (2003), pp. 1234-1241.

View FullText article

DOI, IEEE Explore

Reviews [Write a review of this article]

There are no reviews of this article

Find related articles from these CiteULike users

dcastro

Find related articles with these CiteULike tags

decoder, viterbi

Abstract

Two eight-state 7-bit soft-output Viterbi decoders matched to an EPR4 channel and a rate-8/9 convolutional code are implemented in a 0.18-/spl mu/m CMOS technology. The throughput of the decoders is increased through architectural transformation of the add-compare-select recursion, with a small area overhead. The survivor-path decoding logic of a conventional Viterbi decoder register exchange is adapted to detect the two most likely paths. The 4-mm/sup 2/ chip has been verified to decode at 500 Mb/s with 1.8-V supply. These decoders can be used as constituent decoders for Turbo codes in high-performance applications requiring information rates that are very close to the Shannon limit.

@article{citeulike:2805157, abstract = {Two eight-state 7-bit soft-output Viterbi decoders matched to an EPR4 channel and a rate-8/9 convolutional code are implemented in a 0.18-/spl mu/m CMOS technology. The throughput of the decoders is increased through architectural transformation of the add-compare-select recursion, with a small area overhead. The survivor-path decoding logic of a conventional Viterbi decoder register exchange is adapted to detect the two most likely paths. The 4-mm/sup 2/ chip has been verified to decode at 500 Mb/s with 1.8-V supply. These decoders can be used as constituent decoders for Turbo codes in high-performance applications requiring information rates that are very close to the Shannon limit.}, author = {Yeo, Engling and Augsburger, S. A. and Davis, W. R. and Nikolic, B. }, booktitle = {Solid-State Circuits, IEEE Journal of}, citeulike-article-id = {2805157}, doi = {10.1109/JSSC.2003.813250}, journal = {Solid-State Circuits, IEEE Journal of}, keywords = {decoder, viterbi}, number = {7}, pages = {1234--1241}, posted-at = {2008-05-16 13:03:39}, priority = {2}, title = {A 500-Mb/s soft-output Viterbi decoder}, url = {http://dx.doi.org/10.1109/JSSC.2003.813250}, volume = {38}, year = {2003} }

RIS record

TY - JOUR ID - citeulike:2805157 L3 - citeulike-article-id:2805157 TI - A 500-Mb/s soft-output Viterbi decoder T2 - Solid-State Circuits, IEEE Journal of JF - Solid-State Circuits, IEEE Journal of VL - 38 IS - 7 SP - 1234 EP - 1241 N2 - Two eight-state 7-bit soft-output Viterbi decoders matched to an EPR4 channel and a rate-8/9 convolutional code are implemented in a 0.18-/spl mu/m CMOS technology. The throughput of the decoders is increased through architectural transformation of the add-compare-select recursion, with a small area overhead. The survivor-path decoding logic of a conventional Viterbi decoder register exchange is adapted to detect the two most likely paths. The 4-mm/sup 2/ chip has been verified to decode at 500 Mb/s with 1.8-V supply. These decoders can be used as constituent decoders for Turbo codes in high-performance applications requiring information rates that are very close to the Shannon limit. KW - decoder KW - viterbi AU - Yeo, Engling AU - Augsburger, SA AU - Davis, WR AU - Nikolic, B PY - 2003/// UR - http://dx.doi.org/10.1109/JSSC.2003.813250 ER -

RIS BibTeX