Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^m) in SystemC

@inproceedings{citeulike:2809076, abstract = {In this paper we describe how to model arithmetic circuits over GF(pm) in SystemC. An extension of a GF(2m) multiplier is presented to support GF(pm) arithmetic as well. A full integration in the simulation environment is discussed and the proposed solution can be fully synthesized down to hardware. This finds application in e.g. cryptographic systems. As a case study a Reed-Solomon encoder/decoder system was developed with full GF(pm) encoding/decoding capability. It is shown that the modeling of a HW/SW co-design system in SystemC can improve the speed of simulation by a factor of up to 17.}, author = {Sulflow, Andre and Drechsler, Rolf }, booktitle = {Multiple-Valued Logic, 2007. ISMVL 2007. 37th International Symposium on}, citeulike-article-id = {2809076}, doi = {10.1109/ISMVL.2007.34}, journal = {Multiple-Valued Logic, 2007. ISMVL 2007. 37th International Symposium on}, keywords = {code, decoder, reedsolomon}, pages = {42}, posted-at = {2008-05-18 15:10:56}, priority = {2}, title = {Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^{m}) in SystemC}, url = {http://dx.doi.org/10.1109/ISMVL.2007.34}, year = {2007} }

TY - CONF ID - citeulike:2809076 L3 - citeulike-article-id:2809076 TI - Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^{m}) in SystemC T2 - Multiple-Valued Logic, 2007. ISMVL 2007. 37th International Symposium on JF - Multiple-Valued Logic, 2007. ISMVL 2007. 37th International Symposium on SP - 42 EP - 42 N2 - In this paper we describe how to model arithmetic circuits over GF(pm) in SystemC. An extension of a GF(2m) multiplier is presented to support GF(pm) arithmetic as well. A full integration in the simulation environment is discussed and the proposed solution can be fully synthesized down to hardware. This finds application in e.g. cryptographic systems. As a case study a Reed-Solomon encoder/decoder system was developed with full GF(pm) encoding/decoding capability. It is shown that the modeling of a HW/SW co-design system in SystemC can improve the speed of simulation by a factor of up to 17. KW - code KW - decoder KW - reedsolomon AU - Sulflow, Andre AU - Drechsler, Rolf PY - 2007/// UR - http://dx.doi.org/10.1109/ISMVL.2007.34 ER -