A high-performance and energy-efficient architecture for floating-point based LU decomposition on FPGAs

@inproceedings{citeulike:319435, abstract = {Summary form only given. We first develop a novel architecture for fixed-point LU decomposition of streaming input matrices, on FPGAs. Our architecture, based on a circular linear array, achieves the minimal latency and is resource-efficient. We then extend it, by using a stacked matrices approach, to a floating-point based architecture, which achieves the minimal effective latency. Our design objective was to develop high-throughput and energy-efficient architectures for applications, which require computing LU decomposition. We analyze (1) the impact of high-throughput, pipelined floating-point units (with different depths of pipelining and different performance) on the architecture's performance, and (2) the impact of algorithm level design on the system-wide energy dissipation. We analyze the energy dissipation by capturing algorithm and architectural details of the target FPGA device. We analyze and compare our architecture with a state-of-art architecture implemented on FPGAs with respect to latency, area and energy. Our designs achieve a 10\%-60\% reduction in energy over that of the state-of-art architecture.}, author = {Govindu, G. and Choi, S. and Prasanna, V. and Daga, V. and Gangadharpalli, S. and Sridhar, V. }, citeulike-article-id = {319435}, journal = {Parallel and Distributed Processing Symposium, 2004. Proceedings. 18th International}, keywords = {floating-point, fpga-design, lu-decomposition}, pages = {149+}, posted-at = {2005-09-14 10:27:37}, priority = {3}, title = {A high-performance and energy-efficient architecture for floating-point based LU decomposition on FPGAs}, url = {http://ieeexplore.ieee.org/xpls/abs\_all.jsp?arnumber=1303134}, year = {2004} }

TY - CONF ID - citeulike:319435 L3 - citeulike-article-id:319435 TI - A high-performance and energy-efficient architecture for floating-point based LU decomposition on FPGAs JF - Parallel and Distributed Processing Symposium, 2004. Proceedings. 18th International SP - 149 N2 - Summary form only given. We first develop a novel architecture for fixed-point LU decomposition of streaming input matrices, on FPGAs. Our architecture, based on a circular linear array, achieves the minimal latency and is resource-efficient. We then extend it, by using a stacked matrices approach, to a floating-point based architecture, which achieves the minimal effective latency. Our design objective was to develop high-throughput and energy-efficient architectures for applications, which require computing LU decomposition. We analyze (1) the impact of high-throughput, pipelined floating-point units (with different depths of pipelining and different performance) on the architecture's performance, and (2) the impact of algorithm level design on the system-wide energy dissipation. We analyze the energy dissipation by capturing algorithm and architectural details of the target FPGA device. We analyze and compare our architecture with a state-of-art architecture implemented on FPGAs with respect to latency, area and energy. Our designs achieve a 10%-60% reduction in energy over that of the state-of-art architecture. KW - floating-point KW - fpga-design KW - lu-decomposition AU - Govindu, G AU - Choi, S AU - Prasanna, V AU - Daga, V AU - Gangadharpalli, S AU - Sridhar, V PY - 2004/// UR - http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1303134 ER -