Optimizing hardware function evaluation

@article{citeulike:671504, abstract = {We present a methodology and an automated system for function evaluation unit generation. Our system selects the best function evaluation hardware for a given function, accuracy requirements, technology mapping, and optimization metrics, such as area, throughput, and latency. Function evaluation f(x) typically consists of range reduction and the actual evaluation on a small convenient interval such as [0, /spl pi//2) for sin(x). We investigate the impact of hardware function evaluation with range reduction for a given range and precision of x and f(x) on area and speed. An automated bit-width optimization technique for minimizing the sizes of the operators in the data paths is also proposed. We explore a vast design space for fixed-point sin(x), log(x), and /spl radic/x accurate to one unit in the last place using MATLAB and ASC, a stream compiler for field-programmable gate arrays (FPGAs). In this study, we implement over 2,000 placed-and-routed FPGA designs, resulting in over 100 million application-specific integrated circuit (ASIC) equivalent gates. We provide optimal function evaluation results for range and precision combinations between 8 and 48 bits.}, author = {Lee, D. U. and Gaffar, A. A. and Mencer, O. and Luk, W. }, citeulike-article-id = {671504}, journal = {Computers, IEEE Transactions on}, keywords = {maths-library}, number = {12}, pages = {1520--1531}, posted-at = {2006-05-26 16:20:24}, priority = {2}, title = {Optimizing hardware function evaluation}, url = {http://ieeexplore.ieee.org/xpls/abs\_all.jsp?arnumber=1524934}, volume = {54}, year = {2005} }

TY - JOUR ID - citeulike:671504 L3 - citeulike-article-id:671504 TI - Optimizing hardware function evaluation JF - Computers, IEEE Transactions on VL - 54 IS - 12 SP - 1520 EP - 1531 N2 - We present a methodology and an automated system for function evaluation unit generation. Our system selects the best function evaluation hardware for a given function, accuracy requirements, technology mapping, and optimization metrics, such as area, throughput, and latency. Function evaluation f(x) typically consists of range reduction and the actual evaluation on a small convenient interval such as [0, /spl pi//2) for sin(x). We investigate the impact of hardware function evaluation with range reduction for a given range and precision of x and f(x) on area and speed. An automated bit-width optimization technique for minimizing the sizes of the operators in the data paths is also proposed. We explore a vast design space for fixed-point sin(x), log(x), and /spl radic/x accurate to one unit in the last place using MATLAB and ASC, a stream compiler for field-programmable gate arrays (FPGAs). In this study, we implement over 2,000 placed-and-routed FPGA designs, resulting in over 100 million application-specific integrated circuit (ASIC) equivalent gates. We provide optimal function evaluation results for range and precision combinations between 8 and 48 bits. KW - maths-library AU - Lee, DU AU - Gaffar, AA AU - Mencer, O AU - Luk, W PY - 2005/// UR - http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1524934 ER -