SIMPPL: An Adaptable <emphasis emphasistype="roman">SoC</emphasis> Framework Using a Programmable Controller IP Interface to Facilitate Design Reuse

@article{citeulike:1273110, abstract = {<para> As the complexity of designing system-on-chips increases, so does the need to abstract low-level design issues to improve designer productivity. The reuse of previously designed Intellectual Property (IP) modules is a common form of abstraction used to reduce design time. However, different applications typically use a variety of physical interfaces, communication protocols, and global system-level control for IP modules, which complicates design reuse. In this paper, we describe the SIMPPL system model and an abstraction for IP modules, called the computing element (CE), that facilitate the SoC design for both field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) platforms. The CE abstraction decouples the datapath and system-level communication from the application-specific control to promote design reuse by localizing control redesign of IP for new applications. The SIMPPL model facilitates multi-clock domain SoC designs and expedites system integration by defining the intermodule links and communication protocols. </para>}, author = {Shannon, Lesley and Chow, Paul }, citeulike-article-id = {1273110}, journal = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on}, number = {4}, pages = {377--390}, posted-at = {2007-05-03 04:55:15}, priority = {2}, title = {SIMPPL: An Adaptable <emphasis emphasistype="roman">SoC</emphasis> Framework Using a Programmable Controller IP Interface to Facilitate Design Reuse}, url = {http://ieeexplore.ieee.org/xpls/abs\_all.jsp?arnumber=4162515}, volume = {15}, year = {2007} }

TY - JOUR ID - citeulike:1273110 L3 - citeulike-article-id:1273110 TI - SIMPPL: An Adaptable <emphasis emphasistype="roman">SoC</emphasis> Framework Using a Programmable Controller IP Interface to Facilitate Design Reuse JF - Very Large Scale Integration (VLSI) Systems, IEEE Transactions on VL - 15 IS - 4 SP - 377 EP - 390 N2 - <para> As the complexity of designing system-on-chips increases, so does the need to abstract low-level design issues to improve designer productivity. The reuse of previously designed Intellectual Property (IP) modules is a common form of abstraction used to reduce design time. However, different applications typically use a variety of physical interfaces, communication protocols, and global system-level control for IP modules, which complicates design reuse. In this paper, we describe the SIMPPL system model and an abstraction for IP modules, called the computing element (CE), that facilitate the SoC design for both field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) platforms. The CE abstraction decouples the datapath and system-level communication from the application-specific control to promote design reuse by localizing control redesign of IP for new applications. The SIMPPL model facilitates multi-clock domain SoC designs and expedites system integration by defining the intermodule links and communication protocols. </para> AU - Shannon, Lesley AU - Chow, Paul PY - 2007/// UR - http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4162515 ER -