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mmuecke hdl_tool [16 articles]

Recent papers added to mmuecke library classified by the tag hdl_tool. You can also see everyone's hdl_tool.
  • notes Vector processing as a soft-core CPU accelerator
    (2008), pp. 222-232.
    by Jason Yu, Guy Lemieux, Christpher Eagleston
    posted to electronics_design_automation fpga hdl_tool high_level_synthesis by mmuecke on 2008-03-17 16:04:35 as **
  • notes Stream-Oriented FPGA Computing in the Streams-C High Level Language
    (2000)
    by Maya B Gokhale, Janice M Stone, Jeff Arnold, Mirek Kalinowski
    posted to compiler_design hdl hdl_tool high_level_synthesis parallel_programming vhdl by mmuecke on 2007-10-04 22:40:08 as ****
  • Towards a general framework for FPGA based image processing using hardware skeletons
    Parallel Comput., Vol. 28, No. 7-8. (2002), pp. 1141-1154.
    by K Benkrid, D Crookes, A Benkrid
    posted to compiler_design fpga hdl hdl_tool high_level_synthesis image_processing parallel_programming by mmuecke on 2007-10-02 07:27:48 as *****
  • Hardware Synthesis from Term Rewriting Systems
    (2000), pp. 595-619.
    by James C Hoe, Arvind
    posted to formal_synthesis hdl hdl_tool high_level_synthesis by mmuecke on 2007-09-27 15:11:10 as *****
  • Memory Access Optimization and RAM Inference for Pipeline Vectorization
    Field Programmable Logic and Applications (1999), pp. 61-70.
    by Markus Weinhardt, Wayne Luk
    posted to fpga hdl_tool high_level_synthesis by mmuecke on 2007-06-01 16:54:50 as **
  • IEEE Standard for Property Specification Language (PSL)
    IEEE Std 1850-2005 (2005), pp. 0_1-143.
    posted to hdl hdl_tool vlsi_design by mmuecke on 2007-05-29 12:23:14 as **
  • Automatically Generated CSP Provides Verification for occam-derived Logic Circuits.
    (2005), pp. 180-186.
    by Roger Peel, David
    posted to hdl_tool parallel_programming verification by mmuecke on 2007-05-03 10:41:56 as **
  • notes CHESS: a comprehensive tool for CDFG extraction and synthesis of low power designs from VHDL
    Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on, Vol. 00 (2006), 6 pp..
    by N Ranganathan, R Namballa, N Hanchate
    posted to dfg hdl_tool high_level_synthesis by mmuecke on 2007-05-02 15:48:50 as **
  • CHESS: A TOOL FOR CDFG EXTRACTION AND HIGH-LEVEL SYNTHESIS OF VLSI SYSTEMS
    (July 2003)
    by Ravi K Namballa
    posted to dfg hdl_tool high_level_synthesis vhdl by mmuecke on 2007-05-02 15:36:21 as **
  • notes The Quiny SystemC Front End: Self-Synthesising Designs
    (September 2006), pp. 135-142.
    by Thorsten Schubert, Wolfgang Nebel
    posted to hdl_tool systemc vhdl by mmuecke on 2007-04-30 13:52:55 as read
  • notes GAUT: An architectural synthesis tool for dedicated signal processors
    Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93. European (1993), pp. 14-19.
    by E Martin, O Sentieys, H Dubois, JL Philippe
    posted to dfg hdl_tool high_level_synthesis vhdl by mmuecke on 2007-04-27 14:14:16 as **
  • JHDL-an HDL for reconfigurable systems
    FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on (1998), pp. 175-184.
    by P Bellows, B Hutchings
    posted to hdl hdl_tool language_embedding open_source_eda reconfigurable_platforms by mmuecke on 2007-04-04 13:45:31 as ** along with 1 person and 1 group clarence RC_FCU
  • notes Flow graph representation
    (1986), pp. 503-509.
    by Alex Orailoglu, Daniel D Gajski
    posted to dfg hdl hdl_tool high_level_synthesis survey by mmuecke on 2007-03-29 14:39:08 as **
  • Open HW, open design SW, and the VC ecosystem dilemma
    System-on-Chip for Real-Time Applications, 2005. Proceedings. Fifth International Workshop on (2005), pp. 3-6.
    by JA Carballo
    posted to hdl hdl_tool open_source_eda by mmuecke on 2007-03-19 14:34:53 as **
  • Revolution in electronic EDA education/research: GOSPL
    Microelectronic Systems Education, 2005. (MSE '05). Proceedings. 2005 IEEE International Conference on (2005), pp. 37-38.
    by R Sud, M Chaitanya
    posted to fpga hdl hdl_tool open_source_eda teaching by mmuecke on 2007-03-19 14:25:18 as **
  • notes Integrated techniques for functional and gate-level digital logic simulation
    (1973), pp. 159-172.
    by SA Szygenda, AA Lekkos
    posted to hdl hdl_tool by mmuecke on 2007-03-08 13:08:50 as **
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