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sswanson library [16 articles]

Статьи, недавно добавленные в библиотеку sswanson .
  • A proposal for an architectural approach which apparently solves all known software-based internal computer security problems
    SIGOPS Oper. Syst. Rev., Vol. 18, No. 3. (July 1984), pp. 31-39.
    by Richard L Routh
    posted to architecture computer security by sswanson on 2006-12-05 08:26:48 as **
  • Security design considerations of hardware
    (1984), pp. 253-254.
    by Richard A Smith
    posted to hardware security by sswanson on 2006-12-05 08:24:49 as **
  • Hardware support for code integrity in embedded processors
    (2005), pp. 55-65.
    by Milena Milenkovi&\#263;, Aleksandar Milenkovi&\#263;, Emil Jovanov
    posted to architecture computer hardware security by sswanson on 2006-12-05 08:22:45 as **
  • Towards the issues in architectural support for protection of software execution
    SIGARCH Comput. Archit. News, Vol. 33, No. 1. (March 2005), pp. 6-15.
    by Weidong Shi, Hsien-Hsin S Lee, Chenghuai Lu, Mrinmoy Ghosh
    posted to architecture security by sswanson on 2006-12-05 08:08:35 as **
  • Security in autonomic computing
    SIGARCH Comput. Archit. News, Vol. 33, No. 1. (March 2005), pp. 2-5.
    by David M Chess
    posted to computer security by sswanson on 2006-12-05 08:07:16 as ** along with 1 person and 1 group ddawson Rigi
  • Energy-security tradeoff in a secure cache architecture against buffer overflow attacks
    SIGARCH Comput. Archit. News, Vol. 33, No. 1. (March 2005), pp. 81-89.
    by Koji Inoue
    posted to architecture computer overflow by sswanson on 2006-12-05 08:06:35 as **
  • Using instruction block signatures to counter code injection attacks
    SIGARCH Comput. Archit. News, Vol. 33, No. 1. (March 2005), pp. 108-117.
    by Milena Milenkovi&\#263;, Aleksandar Milenkovi&\#263;, Emil Jovanov
    posted to architecture computer overflow by sswanson on 2006-12-05 08:05:13 as **
  • High efficiency counter mode security architecture via prediction and precomputation
    Computer Architecture, 2005. ISCA '05. Proceedings. 32nd International Symposium on (2005), pp. 14-24.
    by Weidong Shi, HS Lee, M Ghosh, Chenghuai Lu, A Boldyreva
    posted to architecture computer hardware security by sswanson on 2006-12-05 07:56:46 as **
  • Security and protection of data in the IBM System/38
    (1980), pp. 245-252.
    by Viktors Berstis
    posted to architecture computer hardware ibm system38 by sswanson on 2006-12-05 07:37:24 as **
  • Improving Cost, Performance, and Security of Memory Encryption and Authentication
    (2006), pp. 179-190.
    by Chenyu Yan, Daniel Englender, Milos Prvulovic, Brian Rogers, Yan Solihin
    posted to architecture computer encryption hardware memory by sswanson on 2006-12-05 07:35:26 as **
  • ChipLock: support for secure microarchitectures
    SIGARCH Comput. Archit. News, Vol. 33, No. 1. (March 2005), pp. 134-143.
    by Taeho Kgil, Laura Falk, Trevor Mudge
    posted to architecture chiplock computer hardware by sswanson on 2006-12-05 07:33:39 as **
  • SmashGuard: A Hardware Solution to Prevent Security Attacks on the Function Return Address
    Computers, IEEE Transactions on, Vol. 55, No. 10. (2006), pp. 1271-1285.
    by H Ozdoganoglu, TN Vijaykumar, CE Brodley, BA Kuperman, A Jalote
    posted to buffer hardware overflow security by sswanson on 2006-12-05 06:16:27 as ** along with 1 person krisn11
  • Hardware security for software privacy support
    Electronics Letters, Vol. 35, No. 24. (1999), pp. 2096-2098.
    by T Gilmont, JD Legat, JJ Quisquater
    posted to hardware security by sswanson on 2006-12-05 05:45:20 as **
  • Security on FPGAs: State-of-the-art implementations and attacks
    Trans. on Embedded Computing Sys., Vol. 3, No. 3. (August 2004), pp. 534-574.
    by Thomas Wollinger, Jorge Guajardo, Christof Paar
    posted to architecture computer fpga security by sswanson on 2006-11-12 17:16:34 as ** along with 1 person Seenu
  • Implementing 1,024-Bit RSA Exponentiation on a 32-Bit Processor Core
    (2000)
    by BJ Phillips, N Burgess
    posted to 32-bit exponentiation implementation processor rsa by sswanson on 2006-11-12 17:07:37 as **
  • A hardware version of the RSA using the Montgomery's algorithm with systolic arrays
    Integr. VLSI J., Vol. 38, No. 2. (December 2004), pp. 299-307.
    by Ali Z Alkar, Remziye S&\#246;nmez
    posted to algorithm architecture arrays computer hardware montgomerys rsa systolic by sswanson on 2006-11-12 17:04:50 as **
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