High efficiency counter mode security architecture via prediction and precomputation

@inproceedings{citeulike:974389, abstract = {Encrypting data in unprotected memory has gained much interest lately for digital rights protection and security reasons. Counter mode is a well-known encryption scheme. It is a symmetric-key encryption scheme based on any block cipher, e.g. AES. The scheme's encryption algorithm uses a block cipher, a secret key and a counter (or a sequence number) to generate an encryption pad which is XORed with the data stored in memory. Like other memory encryption schemes, this method suffers from the inherent latency of decrypting encrypted data when loading them into the on-chip cache. In this paper, we present a novel technique to hide the latency overhead of decrypting counter mode encrypted memory by predicting the sequence number and pre-computing the encryption pad that we call one-time-pad or OTP. In contrast to the prior techniques of sequence number caching, our mechanism solves the latency issue by using idle decryption engine cycles to speculatively predict and pre-compute OTPs before the corresponding sequence number is loaded. This technique incurs very little area overhead. In addition, a novel adaptive OTP prediction technique is also presented to further improve our regular OTP prediction and precomputation mechanism. This adaptive scheme is not only able to predict encryption pads associated with static and infrequently updated cache lines but also those frequently updated ones as well. Experimental results using SPEC2000 benchmark show an 82\% prediction rate. Moreover, we also explore several optimization techniques for improving the prediction accuracy. Two specific techniques, two-level prediction and context-based prediction are presented and evaluated.}, author = {Shi, Weidong and Lee, H. S. and Ghosh, M. and Lu, Chenghuai and Boldyreva, A. }, citeulike-article-id = {974389}, journal = {Computer Architecture, 2005. ISCA '05. Proceedings. 32nd International Symposium on}, keywords = {architecture, computer, hardware, security}, pages = {14--24}, posted-at = {2006-12-05 07:56:46}, priority = {2}, title = {High efficiency counter mode security architecture via prediction and precomputation}, url = {http://ieeexplore.ieee.org/xpls/abs\_all.jsp?arnumber=1431542}, year = {2005} }

TY - CONF ID - citeulike:974389 L3 - citeulike-article-id:974389 TI - High efficiency counter mode security architecture via prediction and precomputation JF - Computer Architecture, 2005. ISCA '05. Proceedings. 32nd International Symposium on SP - 14 EP - 24 N2 - Encrypting data in unprotected memory has gained much interest lately for digital rights protection and security reasons. Counter mode is a well-known encryption scheme. It is a symmetric-key encryption scheme based on any block cipher, e.g. AES. The scheme's encryption algorithm uses a block cipher, a secret key and a counter (or a sequence number) to generate an encryption pad which is XORed with the data stored in memory. Like other memory encryption schemes, this method suffers from the inherent latency of decrypting encrypted data when loading them into the on-chip cache. In this paper, we present a novel technique to hide the latency overhead of decrypting counter mode encrypted memory by predicting the sequence number and pre-computing the encryption pad that we call one-time-pad or OTP. In contrast to the prior techniques of sequence number caching, our mechanism solves the latency issue by using idle decryption engine cycles to speculatively predict and pre-compute OTPs before the corresponding sequence number is loaded. This technique incurs very little area overhead. In addition, a novel adaptive OTP prediction technique is also presented to further improve our regular OTP prediction and precomputation mechanism. This adaptive scheme is not only able to predict encryption pads associated with static and infrequently updated cache lines but also those frequently updated ones as well. Experimental results using SPEC2000 benchmark show an 82% prediction rate. Moreover, we also explore several optimization techniques for improving the prediction accuracy. Two specific techniques, two-level prediction and context-based prediction are presented and evaluated. KW - architecture KW - computer KW - hardware KW - security AU - Shi, Weidong AU - Lee, HS AU - Ghosh, M AU - Lu, Chenghuai AU - Boldyreva, A PY - 2005/// UR - http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1431542 ER -